James Pucula home

Making a Transistor

I recently finished Code, a book about how to build a computer from first principles. It was excellent, and it left me wanting to know how the physical device works, so I wrote up my study notes on how a transistor works and how it is made.

Disclaimer: These are personal learning notes meant to build intuition, not a fabrication recipe.

Theory

Silicon is a semiconductor, which means it can act like a conductor or an insulator depending on how we treat it. That tunability lets us control how easily electrons leave their atoms or how eagerly nearby atoms accept them.

The band gap is the energy difference between a material's valence band and conduction band. Conductors have overlapping bands or no effective gap, so electrons can move easily. Insulators have a large gap and strongly resist current. Semiconductors have a smaller gap that lets us control their conductivity, which makes them useful for building switches.

The diagram below places silicon on that spectrum.

Band gap comparison between conductors, semiconductors, and insulators

Band-filling diagram by Nanite, CC0.

Building a PN Junction

You can change the concentration of mobile charge carriers by doping silicon—adding a tiny amount of other atoms. Doping introduces energy levels within the existing band structure rather than substantially changing silicon's band gap.

Silicon doping P and N

Silicon-doping diagram by VectorVoyager, CC BY-SA 4.0.

Now place p-type silicon against n-type silicon. Where they meet, electrons diffuse from the n-side into the p-side and recombine with holes. This leaves fixed, positively charged donor ions on the n-side and negatively charged acceptor ions on the p-side, forming a region depleted of mobile carriers.

This charge separation creates an electric field across the junction. The field pushes back on any additional carriers that try to diffuse, so the movement of electrons settles into an equilibrium at a certain distance.

Because the field is produced by displaced charge, you can also view it as a built-in electrical potential (voltage) inside the material.

Energy band diagram of a PN junction at equilibrium

PN-junction equilibrium diagram by TheNoise, CC BY-SA 3.0.


Forward and Reverse Bias

What happens if we try to put electricity through the junction?

First, focus on voltage. Under forward bias, the p-type side is connected to the positive terminal and the n-type side to the negative terminal. Holes and electrons are pushed toward the junction, narrowing the depletion region and lowering the potential barrier so current can flow.

Flip the polarity so the p-type side is negative (reverse bias) and the electric field strengthens. The depletion region widens, the potential barrier increases, and charge carriers have a much harder time crossing.

Try out the slider below: positive values mimic forward bias and you will see the depletion region shrink, while negative values widen it. That one-way behaviour is what makes a diode.

0.1V

No applied bias (0.0 V)
Illustrative depletion width: 160 nm

A small leakage current still flows under reverse bias, and a sufficiently high reverse voltage causes breakdown.


From Diode to MOSFET

Okay, now the MOSFET part.

Place two heavily doped n-type regions inside the p-type silicon. Without any extra help the depletion regions between them block current, so the structure still acts like two back-to-back diodes.

0.0 V

Bias: 0.0 V — both junctions blocking

Next add a metal gate above the surface, separated by a very thin insulating oxide. The field from the gate can influence the silicon, but the oxide stops electrons from freely moving between them. That stack is what gives the MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) its name.

Drive the gate positive relative to the p-type body and the electric field pulls electrons toward the surface. When enough carriers pile up they form a thin inversion layer that behaves like an n-type channel linking the two n+ regions. Remove the voltage and the field dies away, the channel disappears, and the device switches off again.

Tie it all together by biasing the drain positive and raising the gate above threshold. At a sufficiently large drain voltage, the channel pinches off near the drain and the device enters saturation. In that region, it behaves approximately like a voltage-controlled current source—a MOSFET ready to become part of a logic gate or amplifier.

The slider below lets you vary the gate voltage and watch the channel appear.

Gate: 0.0 V — channel off

When the channel is present, electrons travel along the surface instead of fighting the junction. Drop the gate voltage and the depletion region expands again, cutting the path so only leakage trickles through. That simple field-controlled switch is the heart of modern digital logic.

Implementing

With the device physics in place, the next step is turning raw material into the silicon those junctions are built in. The stages below sketch how sand becomes a patterned MOSFET.

Quartz Rock

The starting material is quartz rock, a naturally occurring form of silicon dioxide.

Silicon makes up roughly 28% of the Earth's crust by mass, making it the second most abundant element after oxygen. In practice, producers select high-purity quartz or quartzite with very low concentrations of contaminating elements.

Quartzite forms when quartz-rich sandstone is buried, heated, and recrystallized into dense rock. Semiconductor production begins with deposits selected for their unusually low impurity levels, which makes later purification easier.

Quartzite rock

Quartzite photograph by Gabriel Haute Maurienne, CC BY-SA 4.0.

Metallurgical Silicon

The next step is to strip away the oxygen in silicon dioxide. That happens in an electric arc furnace running around 2,000 °C where quartzite is mixed with high-purity coke (almost pure carbon):

SiO2 + 2 C → Si + 2 CO

This carbothermal reduction yields metallurgical-grade silicon that is roughly 99% pure. Silicon carbide (SiC) can form as a by-product, so operators often run with excess SiO2 to drive the secondary reaction:

2 SiC + SiO2 → 3 Si + 2 CO

Useful, but still far from the “eleven nines” (99.999999999%) purity needed for modern chips.

More on metallurgical-grade silicon

Ultra-Pure Silicon (Polysilicon)

To drive the purity even higher, the metallurgical silicon is converted into volatile chemicals, purified, and then reduced back into solid silicon.

The first step reacts the silicon with hydrogen chloride gas to form trichlorosilane (SiHCl3):

Si + 3 HCl → SiHCl3 + H2

That gas is distilled, then decomposed on heated rods where hydrogen strips the chlorine away:

SiHCl3 + H2 → Si + 3 HCl

Some processes take a detour through silicon tetrachloride (SiCl4) before the final reduction:

SiCl4 + 2 H2 → Si + 4 HCl

Both routes produce shiny polysilicon rods that are vastly purer than the furnace output.

Single-Crystal Silicon (Monosilicon)

The polysilicon still contains many small crystals. The Czochralski process melts that material, dips in a tiny seed crystal, and slowly lifts and rotates it to grow a single large ingot.

Diagram of polycrystalline and single-crystal silicon

Silicon-structure diagram by Cdang, Sbyrnes321, and Rfassbind, CC BY-SA 3.0.

As the ingot grows, the crystal structure rejects many of the remaining impurities. Some facilities run additional zone-refining passes that run heaters along the ingot to push contamination to one end for removal.

Wafer

The ingot is sliced into wafers with a diamond-edged saw and then polished and cleaned to strict specifications.

Stack of polished silicon wafers

Silicon-wafer photograph by Hebbe, public domain.

Fabrication Walkthrough

There are many transistor families, but the metal-oxide-semiconductor FET (MOSFET) dominates modern logic thanks to its density, efficiency, and low cost.

The slideshow below follows a simplified fabrication run. Each step pairs a side view and top view with a quick note about what changed. Use the buttons to step forward or backward.

Fabrication Steps
Step 1

Start with the P-Type Si Wafer

Side View Top View P-Type Silicon

Start with a polished p-type silicon wafer. This is the foundation for every transistor on the die.

Oxide Grown

Side View Top View P-Type Silicon Silicon Dioxide

Grow a 0.5–1 µm silicon dioxide layer (thermal oxide) to insulate the surface. Furnaces run around 900–1200 °C, with oxygen or steam flowing past the wafer.

Photoresist Coated

Side View Top View P-Type Silicon Silicon Dioxide Photoresist

Spin photoresist across the wafer, creating a uniform light-sensitive layer ready for the first mask.

Photoresist Developed

Side View Top View P-Type Silicon Silicon Dioxide Photoresist

After exposure, the developer washes away the exposed positive resist, leaving oxide windows where dopants will eventually be introduced.

Oxide Etched

Side View Top View P-Type Silicon Silicon Dioxide Photoresist

Etch the exposed oxide with a chemistry that ignores both the photoresist and the underlying silicon, opening clean windows down to the substrate.

Photoresist Removed

Side View Top View P-Type Silicon Silicon Dioxide Photoresist

Strip the remaining photoresist with a solvent rinse or a plasma ash step.

Phosphorus Diffused

Side View Top View P-Type Silicon N-Type Silicon Silicon Dioxide Photoresist

Diffuse phosphorus through the openings to create heavily doped n+ source and drain regions. A high-concentration pre-deposition is followed by a drive-in step to set the junction depth.

Oxide Grown

Side View Top View P-Type Silicon N-Type Silicon Silicon Dioxide Photoresist

Grow a fresh oxide to seal the surface. The drive-in step lets the phosphorus spread slightly, but the regions stay highly doped.

PR Applied

Side View Top View P-Type Silicon N-Type Silicon Silicon Dioxide Photoresist

Apply a second photoresist layer so we can pattern the narrow gate region. The spin, bake, align, expose, and develop steps mirror the first lithography cycle.

Photoresist Developed

Side View Top View P-Type Silicon N-Type Silicon Silicon Dioxide Photoresist

After development, only the window above the channel remains open; this is where the thin gate oxide and gate electrode will later be formed.

Oxide Etched

Side View Top View P-Type Silicon N-Type Silicon Silicon Dioxide Photoresist

Etch the oxide in the central opening to prepare a clean channel surface on which a thin, high-quality gate oxide can be grown.

PR Stripped

Side View Top View P-Type Silicon N-Type Silicon Silicon Dioxide Photoresist

Strip the second resist layer, leaving only the patterned oxide and doped regions behind.

Gate Oxide Grown

Side View Top View P-Type Silicon N-Type Silicon Silicon Dioxide Photoresist

Grow a very thin, high-quality gate oxide inside the opening—this dielectric sets the transistor’s threshold and leakage.

Photoresist Added

Side View Top View P-Type Silicon N-Type Silicon Silicon Dioxide Photoresist

Coat the wafer with photoresist again to prepare the contact cuts that will connect metal to the source and drain.

Photoresist Developed

Side View Top View P-Type Silicon N-Type Silicon Silicon Dioxide Photoresist

Develop the resist to expose the contact holes while keeping the surrounding areas protected.

Oxide Etched

Side View Top View P-Type Silicon N-Type Silicon Silicon Dioxide Photoresist

Etch the oxide inside those tiny windows so the future metal can reach the doped silicon regions.

Photoresist Removed

Side View Top View P-Type Silicon N-Type Silicon Silicon Dioxide Photoresist

After etching, strip the resist once more to leave clean contact holes ready for metallization.

Aluminium Film Deposited

Side View Top View P-Type Silicon N-Type Silicon Silicon Dioxide Photoresist Aluminium

Blanket the wafer with aluminium by evaporation or sputtering so there is metal everywhere the contacts will later be patterned.

Photoresist Patterned

Side View Top View P-Type Silicon N-Type Silicon Silicon Dioxide Photoresist Aluminium

Spin-coat photoresist on top of the aluminium so the upcoming mask can define the wiring pattern.

Photoresist Applied

Side View Top View P-Type Silicon N-Type Silicon Silicon Dioxide Photoresist Aluminum

Expose and develop the resist so only the future interconnect lines stay protected.

Aluminium Etched

Side View Top View P-Type Silicon N-Type Silicon Silicon Dioxide Photoresist Aluminium

Etch the exposed aluminium, leaving behind only the metal protected by resist.

Photoresist Removed

Side View Top View P-Type Silicon N-Type Silicon Silicon Dioxide Photoresist Aluminium

Strip the final resist to reveal finished metal contacts and interconnects.

From raw quartz to patterned aluminium, every step above protects or exposes tiny regions so dopants and metals end up where the circuit diagram needs them. Once you have a working MOSFET, millions or billions of copies can become logic gates, memory cells, and the rest of a computer.

Resources

Thank you for reading. I enjoyed making this summary and learnt so much.